Multiprocessor system architectures for distributed processing often employ shared common memory between processors. This may be accomplished in a multiprocessor system using multiport memories, or architectures including cross bar switches, a time-shared common bus, or a dual-bus structure.
A multiport memory system employs separate buses between each memory module and each processor. Each processor bus is physically connected to each memory module. Each memory module is multiported, each port accommodating one of the buses. Each memory module may have internal control logic to determine which port will have access to memory at any given time. Memory access conflicts are resolved by assigning priorities to each memory port. High transfer rates can be achieved because of the multiple paths between processors and memory.
A multiprocessor cross bar switch architecture provides switched cross points placed at intersections between processor buses and memory module paths. Each switch point has control logic to set up the physical transfer path between a processor and memory. The control logic examines the address that has been placed on the bus to determine whether its particular module is being addressed and also to resolve multiple requests for access to the same memory module on a predetermined priority basis.
In a multiprocessor time-shared architecture, a number of processors may be connected through a common path to a memory unit. In such a system only one processor can communicate with the memory at any given time. Transfer operations are controlled by the processor that is in control of the bus at any given time. Any other processor wishing to initiate a transfer must first determine the availability status of the bus, and only after the bus become available can the processor address the memory unit to initiate the transfer. The system may exhibit memory access conflicts since one common bus is shared by all processors. Memory contention must be resolved with a bus controller that establishes priorities among the requesting units. The time-shared architecture is disadvantageous because when one processor is communicating with the memory, all other processors are either busy with internal operations or must be idle waiting for the bus.
A more efficient architecture than the time-shared common bus multiprocessor architecture is a dual-bus multiprocessor organization in which a number of local buses are each connected to a local memory and to one or more processors. System bus controllers associated with each local bus are used to link each local bus to a common system bus. In most designs, the devices connected to the local bus are available to the local processors only. Memory connected to the common system bus is shared by all processors. The system may be configured to permit devices attached to the local bus to be accessed by processors on other local buses. Only one processor can communicate with the shared memory and any other common resources through the system bus at any given time. The other processors on the local buses are kept busy communicating with their local memory and local devices. Although such a system qualifies as a multiprocessor system, it can also be classified more correctly as a multiple computer system. This is because when a processor, memory, and other devices are connected together on a local bus the local group constitutes a computer system in its own right.
For safety reasons many systems are organized in a redundant fashion having multiple computers operating independently. Other redundant systems permit semiautonomous operation of distributed processors and provide that a failed processor or related device can be severed from the system without catastrophically degrading overall system operation.
Distributed multiple processor systems must operate semiautonomously to obtain maximum efficiency. To acheive near independence despite their interconnected communication links they must utilize some means of transferring data between distributed processors which avoids processor overhead. This may be acheived to some degree by using multiport memory units having physically isolated address and data input buses for each port. Hand-shaking between processors provides the necessary control for transferring data between processors using the multiport memory unit as an intermediary. Although the use of shared memory provides a degree of addressing freedom, only one processor is allowed access to the memory at any given point in time. This restriction may not be acceptable for some system design requirements, i.e., it may not be acceptable to deprive a processor of free access to memory.
A partial solution to the problem of system requirements not permitting the "wait" states dictated by shared memory is the use of a first-in-first-out (FIFO) buffer between processors. In this way no processor is deprived of immediate access to memory and freedom of data flow is therefore ensured. Data may be input and output at two different rates and the output data are always in the same order in which data entered the buffer. For bidirectional flow FIFO buffers may be employed in both directions. However, the freedom of addressing acheived with shared memory is lost in the FIF buffer solution.
In addition to the individual advantages of the shared memory and FIFO buffer approaches described above, both approaches still suffer, despite the isolation provided by additional memory, from a certain lack of processing independence which is most desirable. In the case of a shared memory the denial of access to a processor at any given time results in undesirable wait states which decrease system efficiency. In the case of CPU buffered by FIFOs the information which may be provided by shared addressing is not available. I.e., while a CPU can control the position assignment of data when writing into a FIFO, it has no control of the assignment of data when reading from a FIFO. In other words, the reading CPU may have to read data of no present interest before getting to the stored position of present interest.
The desirability of providing more efficient processing for distributed processors becomes more important as the complexity of the system increases. As the number of processors increases and the intercommunication requirements become more complex, the disadvantageous opportunities for creating undesirable wait states also increase. Thus, a means of increasing processing efficiency while maintaining or increasing relative semi-autonomous operation is needed.